1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, aspects of the present invention relate to a method of manufacturing a semiconductor device that includes a dielectric layer, which includes metal oxide having a high dielectric constant, on a charge-trapping layer.
2. Description of the Related Art
Generally, a semiconductor memory device may be classified as either a volatile memory device, such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, etc., that loses data over time, or a non-volatile memory device that continuously stores data regardless of the passage of time. Data is rapidly inputted/outputted into/from the volatile memory device. In contrast, data is slowly inputted/outputted into/from the non-volatile memory device. The non-volatile memory device may include an electrically erasable programmable read-only memory (EEPROM), a flash EEPROM memory device, etc., capable of electrically inputting/outputting data. The flash EEPROM memory device electrically controls input/output of data using Fowler-Nordheim (F-N) tunneling or channel hot electron injection to perform programming and erasing operations. The flash memory device may be classified as a floating gate-type non-volatile memory device, a silicon-oxide-nitride-oxide-silicon (SONOS)-type non-volatile memory device, or a metal-oxide-nitride-oxide-silicon (MONOS)-type non-volatile memory device.
A unit cell of the SONOS-type or the MONOS-type non-volatile memory device may include a tunnel oxide layer formed on a semiconductor substrate, a charge-trapping layer including silicon nitride for trapping electrons from a channel region, a dielectric layer formed on the charge-trapping layer, a gate electrode structure including a conductive layer that is formed on the dielectric layer, and a spacer formed on a sidewall of the gate electrode structure.
As semiconductor devices have become highly integrated, a stack-type memory device has been developed. The stack-type memory device may include a multi-channel layer formed by vertically stacking a plurality of non-volatile memory cells, and a deep contact for electrically coupling between the channel layers.
Here, when the MONOS-type stack memory device has dual channel regions, two semiconductor substrates may be vertically attached to each other.
According to a method of manufacturing the MONOS-type stack memory device, a plurality of memory cells is formed on a first semiconductor substrate. A second semiconductor substrate is attached to the first semiconductor substrate. Here, before attaching the second semiconductor substrate to the first semiconductor substrate, a hydrogen ion implantation region in the second semiconductor substrate may be thermally treated to separate a portion of the second semiconductor substrate from the remainder of the second semiconductor substrate. A plurality of memory cells is formed on the second semiconductor substrate, after the second semiconductor substrate is attached to the first semiconductor substrate. Thus, the process for forming the memory cells on the second semiconductor substrate is performed under a condition in which the first semiconductor substrate and the second semiconductor substrate are attached to each other.
However, when gate electrode structures of the memory cells on the second semiconductor substrate are formed as the MONOS-type, it may be difficult to perform the thermal treatment because of a thermal diffusion of impurity ions in the first semiconductor substrate generated when forming the dielectric layer that includes the metal oxide having the high dielectric constant. For example, to densify a crystalline structure of the dielectric layer including aluminum oxide (Al2O3), the dielectric layer may be thermally treated at a high temperature of about 900° C. to about 1,100° C. Here, the impurity ions in the impurity regions of the first semiconductor substrate may thermally diffuse when temperatures are in the high temperature range. Therefore, since it may be very difficult to form the channel region, operational characteristics of the semiconductor device may be deteriorated.
In contrast, when the thermal treatment is performed at a relatively low temperature to maintain an ion doping profile of the impurity regions in the first semiconductor substrate, the crystalline structure of the dielectric layer may become sparse, so that the memory cell of the semiconductor device may have low reliability. Thus, it may be required to improve the operational characteristics of the unit cell when the semiconductor device has the stack-type memory cell.